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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5505/6/7/8 very low power, 16-bit and 20-bit a/d converters features l very low power consumption - single supply +5 v operation: 1.7 mw - dual supply 5 v operation: 3.2 mw l offers superior performance to vfcs and multi-slope integrating adcs l differential inputs - single channel (cs5507/8) and four-channel (cs5505/6) pseudo-differential versions l either 5 v or 3.3 v digital interface l linearity error: - 0.0015% fs (16-bit cs5505/7) - 0.0007% fs (20-bit cs5506/8) l output update rates up to 100 sps l flexible serial port l pin-selectable unipolar/bipolar ranges description the cs5505/6/7/8 are a family of low power cmos a/d converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes. the cs5507/8 have single-channel differential analog and reference inputs while the cs5505/6 have four pseudo-differential analog input channels. the cs5505/7 have a 16-bit output word. the cs5506/8 have a 20-bit output word.the cs5505/6/7/8 sample upon command up to 100 sps . the on-chip digital filter offers superior line rejection at 50 and 60 hz when the device is operated from a 32.768 khz clock (output word rate = 20 sps ). the cs5505/6/7/8 include on-chip self-calibration cir- cuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. the cs5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers or syn- chronous serial ports of industry-standard microcontrollers. ordering information see page 30. i &6 '*1' 9' 6&/. 6'$7$ '5'< &$/ %383 &219 ;,1 $,1 $,1 ;287 9$ 9$ 08; wk2ughu 'howd6ljpd 0rgxodwru 'ljlwdo )lowhu &doleudwlrq & 6huldo ,qwhuidfh /rjlf 26& &doleudwlrq65$0 'liihuhqwldo $ $ $,1 $,1 $,1 95() 95() 9rowdjh5hihuhqfh 95()287 06/3 &6%,7$1'&6%,76+2:1 mar 95 ds59f4 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5505/6/7/8 very low-power, 16-bit & 20-bit a/d converters aug ?05 ds59f5 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cdb5505/6/7/8 evaluation board for cs 5505/6/7/8 series of adcs aug ?05 ds59db3 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5505/6/7/8 very low-power, 16-bit & 20-bit a/d converters aug ?05 ds59f5
analog characteristics (t a = t min to t max ; va+ = 5v 10%; va- = -5v 10%; vd+ = 3.3v 5%; vref+ = 2.5v(external); vref- = 0v; f clk = 32.768khz; bipolar mode; r source = 1k ? with a 10nf to agnd at ain; analog input channel ain1+; ain- = agnd; unless otherwise specified.) (notes 1, 2) cs5505/7-a cs5507-s parameter* min typ max min typ max units specified temperature range -40 to +85 -55 to +125 c accuracy linearity error - 0.0015 0.003 - 0.0015 0.003 %fs differential nonlinearity - 0.25 0.5 - 0.25 0.5 lsb 16 full scale error (note 3) - 0.25 2 - 0.5 2 lsb 16 full scale drift (note 4) - 0.5 -- 2 - lsb 16 unipolar offset (note 3) - 0.5 2 - 1 4 lsb 16 unipolar offset drift (note 4) - 0.5 -- 1 - lsb 16 bipolar offset (note 3) - 0.25 1 - 0.5 2 lsb 16 bipolar offset drift (note 4) - 0.25 -- 0.5 - lsb 16 noise (referred to output) - 0.16 - - 0.16 - lsb- rms 16 notes: 1. the ain pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. both source resistance and shunt capacitance are therefore critical in determining the cs5505/6/7/8s source impedance requirements. for more information refer to the text section analog input impedance considerations. 2. specifications guaranteed by design, characterization and/or test. 3. applies after calibration at the temperature of interest. 4. total drift over the specified temperature range since calibration at power-up at 25 c. recalibration at any temperature will remove these errors. specifications are subject to change without notice. * refer to the specification definitions immediately following the pin description section. unipolar mode bipolar mode mv lsbs % fs ppm fs lsbs % fs ppm fs 10 0.26 0.0004 4 0.13 0.0002 2 19 0.50 0.0008 8 0.26 0.0004 4 38 1.00 0.0015 15 0.50 0.0008 8 76 2.00 0.0030 30 1.00 0.0015 15 152 4.00 0.0061 61 2.00 0.0030 30 vref = 2.5v cs5505/7; 16-bit unit conversion factors cs5505/6/7/8 2 ds59f4 cs5505/6/7/8 2 ds59f5
analog characteristics (t a = t min to t max ; va+ = 5v 10%; va- = -5v 10%; vd+ = 3.3v 5%; vref+ = 2.5v (external); vref- = 0v; f clk = 32.768khz; bipolar mode; r source = 1k ? with a 10nf to agnd at ain; analog input channel ain1+; ain- = agnd; unless otherwise specified.) (notes 1, 2) cs5506/8-b cs5508-s parameter* min typ max min typ max units specified temperature range -40 to +85 -55 to +125 c accuracy linearity error - 0.0007 0.0015 - 0.0015 0.003 %fs differential nonlinearity (no missing codes) 20 - - 20 - - bits full scale error (note 3) - 4 32 - 8 32 lsb 20 full scale drift (note 4) - 8 -- 32 - lsb 20 unipolar offset (note 3) - 8 32 - 16 64 lsb 20 unipolar offset drift (note 4) - 8 -- 16 - lsb 20 bipolar offset (note 3) - 4 16 - 8 32 lsb 20 bipolar offset drift (note 4) - 4 -- 8 - lsb 20 noise (referred to output) - 2.6 - - 2.6 - lsb- rms 20 unipolar mode bipolar mode mv lsbs % fs ppm fs lsbs % fs ppm fs 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91 vref = 2.5v cs5506/8; 20-bit unit conversion factors dynamic characteristics parameter symbol ratio units modulator sampling frequency f s f clk /2 hz output update rate (conv = 1) f out f clk /1622 sps filter corner frequency f -3db f clk /1928 hz settling time to 1 ? 2 lsb (fs step) t s 1/f out s cs5505/6/7/8 ds59f4 3 cs5505/6/7/8 ds59f5 3
analog characteristics (t a = t min to t max ; va+ = 5v 10%; va- = -5v 10%; vd+ = 3.3v 5%; vref+ = 2.5v (external); vref- = 0v; f clk = 32.768khz; bipolar mode; r source = 1k ? with a 10nf to agnd at ain; analog input channel ain1+; ain- = agnd; unless otherwise specified.) (notes 1, 2) cs5505/7 cs5506/8 cs5507/8-s parameter* min typ max min typ max units specified temperature range -40 to +85 -55 to +125 c analog input analog input range: unipolar (vain+)-(vain-) bipolar (note 5) 0 to +2.5 2.5 0 to +2.5 2.5 volts volts common mode rejection: dc 50, 60 hz (note 6) - 120 105 - - - - 120 105 - - - db db off channel isolation - 120 - - 120 - db input capacitance - 15 - - 15 - pf dc bias current (note 1) - 5 - - 5 - na voltage reference (output) vrefout voltage - (va+)-2.5 - - (va+)-2.5 - volts vrefout voltage tolerance - - 4.0 - - 4.0 % vrefout voltage temperature coefficient - 60 - - 60 - ppm/ c vrefout line regulation - 1.5 - - 1.5 - mv/volt vrefout output voltage noise 0.1 to 10 hz -50- -50- v p-p vrefout: source current sink current - - - - 3 50 - - - - 3 50 a a power supplies dc power supply currents: i total i analog i digital - - - 340 300 40 450 - - - - - 340 300 40 450 - - a a a power dissipation: (note 7) sleep inactive sleep active - - 3.2 5 4.5 10 - - 3.2 10 4.5 25 mw w power supply rejection: positive supplies negative supplies - - 80 80 - - - - 80 80 - - db db notes: 5. common mode voltage may be at any value as long as ain+ and ain- remain within the va+ and va- supply voltages. 6. xin = 32.768 khz. guaranteed by design and / or characterization. 7. all outputs unloaded. all inputs cmos levels. sleep mode controlled by m/slp pin. sleep active = m/slp pin at (vd+)/2 input level. cs5505/6/7/8 4 ds59f4 cs5505/6/7/8 4 ds59f5
5v digital characteristics (t a = t min to t max ; va+vd+ = 5v 10%; va-= -5v 10%; dgnd = 0.) all measurements below are performed under static conditions. (note 2) parameter symbol min typ max units high-level input voltage: xin m/slp all pins except xin and m/slp v ih v ih v ih 3.5 0.9vd+ 2.0 - - - - - - v v v low-level input voltage: xin m/slp all pins except xin and m/slp v il v il v il - - - - - - 1.5 0.1vd+ 0.8 v v v m/slp sleep active threshold (note 8) v slp 0.45vd+ 0.5vd+ 0.55vd+ v high-level output voltage (note 9) v oh (vd+)-1.0 - - v low level output voltage i out = 1.6 ma v ol --0.4v input leakage current i in -110 a 3-state leakage current i oz -- 10 a digital output pin capacitance c out -9-pf notes: 8. under normal operation this pin should be tied to vd+ or dgnd. anytime the voltage on the m/slp pin enters the sleep active threshold range the device will enter the power down condition. returning to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse of the wake-up period. 9. i out = -100 a. this guarantees the ability to drive one ttl load. (v oh = 2.4v @ i out = -40 a). 3.3v digital characteristics (t a = t min to t max ; va+ = 5v 10%; vd+ = 3.3v 5%; va-= -5v 10%; dgnd = 0.) all measurements below are performed under static conditions. (note 2) parameter symbol min typ max units high-level input voltage: xin m/slp all pins except xin and m/slp v ih vih v ih 0.7vd+ 0.9vd+ 0.6vd+ - - - - - - v v v low-level input voltage: xin m/slp all pins except xin and m/slp v il vil v il - - - - - - 0.3vd+ 0.1vd+ 0.16vd+ v v v m/slp sleep active threshold (note 8) v slp 0.43vd+ 0.45vd+ 0.47vd+ v high-level output voltage i out = -400 a v oh (vd+)-0.3 - - v low level output voltage i out = 400 a v ol --0.3v input leakage current i in -110 a 3-state leakage current i oz -- 10 a digital output pin capacitance c out -9-pf cs5505/6/7/8 ds59f4 5 cs5505/6/7/8 ds59f5 5
5v switching characteristics (t a = t min to t max; va+, vd+ = 5v 10%; va- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units master clock frequency: internal oscillator: -a,b -s external clock: xin or f clk 30.0 30.0 30 32.768 32.768 - 53.0 34.0 163 khz khz khz master clock duty cycle 40 - 60 % rise times: any digital input (note 10) any digital output t rise - - - 50 1.0 - s ns fall times: any digital input (note 10) any digital output t fall - - - 20 1.0 - s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal=32.768 khz (note 12) t osu - 500 - ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal = 1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl --2/f clk+200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion set up time a0, a1 to conv high t sac 50 - - ns hold time a0, a1 after conv high t hca 100 - - ns conv pulse width t cpw 100 - - ns conv high to start of conversion t scn --2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to end of conversion (note 15) t con - 1624/f clk -s notes: 10. specified using 10% and 90% points on waveform of interest. 11. an internal power-on-reset is activated whenever power is applied to the device, or when coming out of a sleep state. 12. oscillator start-up time varies with the crystal parameters. this specification does not apply when using an external clock source. 13. the wake-up period begins once the oscillator starts; or when using an external f clk , after the power-on reset time elapses. 14. calibration can also be initiated by pulsing cal high while conv=1. 15. conversion time will be 1622/f clk if conv remains high continuously. cs5505/6/7/8 6 ds59f4 cs5505/6/7/8 6 ds59f5
3.3v switching characteristics (t a = t min to t max va+ = 5v 10%; vd+ = 3.3v 5%; va- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; cl = 50 pf.) (note 2) parameter symbol min typ max units master clock frequency: internal oscillator: -a,b -s external clock: xin or f clk 30.0 30.0 30 32.768 32.768 - 53.0 34.0 163 khz khz khz master clock duty cycle 40 - 60 % rise times: any digital input (note 10) any digital output t rise - - - 50 1.0 - s ns fall times: any digital input (note 10) any digital output t fall - - - 20 1.0 - s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal=32.768 khz (note 12) t osu - 500 - ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal = 1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl --2/f clk+ 200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion set up time a0, a1 to conv high t sac 50 - - ns hold time a0, a1 after conv high t hca 100 - - ns conv pulse width t cpw 100 - - ns conv high to start of conversion t scn --2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to end of conversion (note 15) t con - 1624/f clk -s cs5505/6/7/8 ds59f4 7 cs5505/6/7/8 ds59f5 7
t ccw xin calibration standby standby t scl t cal xin/2 state cal conv figure 1. calibration timing (not to scale) t buh xin xin/2 conversion standby standby conv state t sac t hca a0, a1 t scn t con drdy bp/up t bus t cpw figure 2. conversion timing (not to scale) cs5505/6/7/8 8 ds59f4 cs5505/6/7/8 8 ds59f5
5v switching characteristics (t a = t min to t max; va+, vd+ = 5v 10%; va- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units ssc mode (m/slp = vd+) access time: cs low to sdata out (drdy = low) drdy falling to msb (cs = low) t csd1 t dfd - - - 2/f clk 2/fclk 3/f clk ns ns sdata delay time: sclk falling to next sdata bit t dd1 - 80 250 ns sclk delay time sdata msb bit to sclk rising t cd1 -1/f clk -ns serial clock (out) pulse width high pulse width low t ph1 t pl1 - - 1/f clk 1/f clk - - ns ns output float delay: cs high to output hi-z (note 16) sclk rising to sdata hi-z t fd1 t fd2 - - - 1/f clk 2/f clk - ns ns sec mode (m/slp = dgnd) serial clock (in) f sclk 0-2.5mhz serial clock (in) pulse width high pulse width low t ph2 t pl2 200 200 - - - - ns ns access time: cs low to data valid (note 17) t csd2 - 60 200 ns maximum delay time: (note 18) sclk falling to new sdata bit t dd2 - 150 310 ns output float delay: cs high to output hi-z (note 16) sclk falling to sdata hi-z t fd3 t fd4 - - 60 160 150 300 ns ns notes: 16. if cs is returned high before all data bits are output, the sdata and sclk outputs will complete the current data bit and then go to high impedance. 17. if cs is activated asynchronously to drdy, cs will not be recognized if it occurs when drdy is high for 2 clock cycles. the propagation delay time may be as great as 2 f clk cycles plus 200 ns. to guarantee proper clocking of sdata when using asynchronous cs, sclk(i) should not be taken high sooner than 2 f clk + 200 ns after cs goes low. 18. sdata transitions on the falling edge of sclk. note that a rising sclk must occur to enable the serial port shifting mechanism before falling edges can be recognized. cs5505/6/7/8 ds59f4 9 cs5505/6/7/8 ds59f5 9
3.3v switching characteristics (t a = t min to t max va+ = 5v 10%; vd+ = 3.3v 5%; va- = -5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units ssc mode (m/slp = vd+) access time: cs low to sdata out (drdy = low) drdy falling to msb (cs = low) t csd1 t dfd - - - 2/f clk 2/fclk 3/f clk ns ns sdata delay time: sclk falling to next sdata bit t dd1 - 265 400 ns sclk delay time sdata msb bit to sclk rising t cd1 -1/f clk -ns serial clock (out) pulse width high pulse width low t ph1 t pl1 - - 1/f clk 1/f clk - - ns ns output float delay: cs high to output hi-z (note 16) sclk rising to sdata hi-z t fd1 t fd2 - - - 1/f clk 2/f clk - ns ns sec mode (m/slp = dgnd) serial clock (in) f sclk 0 - 1.25 mhz serial clock (in) pulse width high pulse width low t ph2 t pl2 200 200 - - - - ns ns access time: cs low to data valid (note 17) t csd2 - 100 200 ns maximum delay time: (note 18) sclk falling to new sdata bit t dd2 - 400 600 ns output float delay: cs high to output hi-z (note 16) sclk falling to sdata hi-z t fd3 t fd4 - - 70 320 150 500 ns ns cs5505/6/7/8 10 ds59f4 cs5505/6/7/8 10 ds59f5
xin xin/2 conv state t cd1 t dd1 msb msb-1 pl1 t ph1 t fd2 t lsb+1 lsb conversion2 state (conv held high) sdata(o) sclk(o) conversion1 cs drdy standby standby conversion conversion hi-z hi-z hi-z hi-z t csd1 figure 3. timing relationships; ssc mode (not to scale) drdy cs sclk(i) msb-1 msb msb-2 sdata(o) hi-z msb-1 msb lsb+2 lsb+1 lsb drdy cs sclk(i) sdata(o) hi-z t fd3 t csd2 t dd2 t ph2 t pl2 t fd4 t dd2 t csd2 figure 4. timing relationships; sec mode (not to scale) cs5505/6/7/8 ds59f4 11 cs5505/6/7/8 ds59f5 11
recommended operating conditions (dgnd = 0v) (note 19) parameter symbol min typ max units dc power supplies: positive digital (va+)-(va-) positive analog negative analog vd+ v diff va+ va- 3.15 4.5 4.5 0 5.0 10 5.0 -5.0 5.5 11 11 -5.5 v v v v analog reference voltage (note 20) (vref+)-(vref-) 1.0 2.5 3.6 v analog input voltage: (note 21) unipolar bipolar vain vain 0 -((vref+)-(vref-)) - - (vref+)-(vref-) +((vref+)-(vref-)) v v notes: 19. all voltages with respect to ground. 20. the cs5505/6/7/8 can be operated with a reference voltage as low as 100 mv; but with a corresponding reduction in noise-free resolution. the common mode voltage of the voltage reference may be any value as long as +vref and -vref remain inside the supply values of va+ and va-. 21. the cs5505/6/7/8 can accept input voltages up to the analog supplies (va+ and va-). in unipolar mode the cs5505/6/7/8 will output all 1s if the dc input magnitude ((ain+)-(ain-)) exceeds ((vref+)-(vref-)) and will output all 0s if the input becomes more negative than 0 volts. in bipolar mode the cs5505/6/7/8 will output all 1s if the dc input magnitude ((ain+)-(ain-)) exceeds ((vref+)-(vref-)) and will output all 0s if the input becomes more negative in magnitude than -((vref+)-(vref-)). absolute maximum ratings* parameter symbol min typ max units dc power supplies: digital ground (note 22) positive digital (note 23) positive analog negative analog (va+)-(va-) (va+)-(vd+) dgnd vd+ va+ va- v diff1 v diff2 -0.3 -0.3 -0.3 +0.3 -0.3 -0.3 - - - - - - (vd+)-0.3 6.0 or va+ 12.0 -6.0 12.0 12.0 v v v v v v input current, any pin except supplies (notes 24, 25) i in -- 10 ma analog input voltage ain and vref pins v ina (va-)-0.3 - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -55 - 125 c storage temperature t stg -65 - 150 c notes: 22. no pin should go more positive than (va+)+0.3v. 23. vd+ must always be less than (va+)+0.3 v,and can never exceed 6.0v. 24. applies to all pins including continuous overvoltage conditions at the analog input (ain) pin. 25. transient currents of up to 100ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. * warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs5505/6/7/8 12 ds59f4 cs5505/6/7/8 12 ds59f5
general description the cs5505/6/7/8 are very low power mono- lithic cmos a/d converters designed specifically for measurement of dc signals. the cs5505/7 are 16-bit converters (a four channel and a single channel version). the cs5506/8 are 20-bit converters (a four channel and a single channel version). each of the devices includes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with sram, a digital filter and a serial interface. the cs5505 and cs5506 include a four channel pseudo-differential (all four channels have the same reference measurement node) multiplexer. the cs5505/6/7/8 include an on-chip reference but can also utilize an off-chip reference for pre- cision applications. the cs5505/6/7/8 can be used to measure either unipolar or bipolar sig- nals. the devices use self-calibration to insure excellent offset and gain accuracy. the cs5505/6/7/8 are optimized to operate from a 32.768 khz crystal but can be driven by an external clock whose frequency is between 30 khz and 163 khz. when the digital filter is operated with a 32.768 khz clock, the filter has zeros precisely at 50 and 60 hz line frequencies and multiples thereof. the cs5505/6/7/8 use a "start convert" com- mand to latch the input channel selection and to start a convolution cycle on the digital filter. once the filter cycle is completed, the output port is updated. when operated with a 32.768 khz clock the adc converts and updates its output port at 20 samples/sec. the throughput rate per channel is the output update rate divided by the number of channels being multi- plexed. the output port includes a serial interface with two modes of operation. the cs5505/6/7/8 can operate from dual polar- ity power supplies (+5 and -5), from a single +5 volt supply, or with +10 volts on the analog and +5 on the digital. they can also operate with dual polarity (+5 and -5), or from a single +5 volt supply on the analog and + 3.3 on the digi- tal. theory of operation for the cs5505/6/7/8 the front page of this data sheet illustrates the block diagram of the cs5505/6. basic converter operation the cs5505/6/7/8 a/d converters have four op- erating states. these are start-up, calibration, conversion and sleep. when power is first ap- plied, the device enters the start-up state. the first step is a power-on reset delay of about 10 ms which resets all of the logic in the device. to proceed with start-up, the oscillator must then begin oscillating. after the power-on reset the device enters the wake-up period for 1800 clock cycles after clock is present. this allows the delta-sigma modulator and other circuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. during the 1800 cycle wake-up period, the de- vice can accept an input command. execution of this command will not occur until the complete wake-up period elapses. if no command is given, the device enters the standby mode. calibration after the initial application of power, the cs5505/6/7/8 must enter the calibration state prior to performing accurate conversions. during calibration, the chip executes a two-step process. the device first performs an offset calibration and then follows this with a gain calibration. the two calibration steps determine the zero ref- erence point and the full scale reference point of the converters transfer function. from these points it calibrates the zero point and a gain cs5505/6/7/8 ds59f4 13 cs5505/6/7/8 ds59f5 13
slope to be used to properly scale the output digital codes when doing conversions. the calibration state is entered whenever the cal and conv pins are high at the same time. the state of the cal and conv pins at power- on and when coming out of sleep are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. note that any time conv transitions from low to high, the multiplexer inputs a0 and a1 are latched internal to the cs5505 and cs5506 de- vices. these latched inputs select the analog input channel which will be used once conver- sion commences. if cal and conv become active (high) during the 1800 clock cycle wake-up time, the con- verter will wait until the wake-up period elapses before executing the calibration. if the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately. the cali- bration lasts for 3246 clock cycles. calibration coefficients are then retained in the sram (static ram) for use during conversion. at the end of the calibration cycle, the on-chip microcontroller checks the logic state of the conv signal. if the conv input is low the de- vice will enter the standby mode where it waits for further instruction. if the conv signal is high at the end of the calibration cycle, the con- verter will enter the conversion state and perform a conversion on the input channel which was selected when conv transitioned from low to high. the cal signal can be returned low any time after calibration is initiated. conv can also be returned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. if conv is taken low and then high again with cal high while the con- verter is calibrating, the device will interrupt the current calibration cycle and start a new one. if cal is taken low and conv is taken low and then high during calibration, the calibration cy- cle will continue as the conversion command is disregarded. the states of a0, a1 and bp/ up are not important during calibrations. if an "end of calibration" signal is desired, pulse the cal signal high while leaving the conv signal high continuously. once the calibration is completed, a conversion will be performed. at the end of the conversion, drdy will fall to in- dicate the first valid conversion after the calibration has been completed. see understanding converter calibration for de- tails on how the converter calibrates its transfer function. conversion the conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. if conv is taken high to initiate a calibration cycle ( cal also high), and remains high until the calibration cy- cle is completed (cal is taken low after conv transitions high), the converter will begin a con- version upon completion of the calibration period. the device will perform a conversion on the input channel selected by the a0 and a1 in- puts when conv transitioned high. table 1 indicates the multiplexer channel selection truth table for a0 and a1. the a0 and a1 inputs are latched internal to the 4-channel devices (cs5505/6) when conv rises. a0 and a1 have internal pull-down cir- cuits which default the multiplexer to channel a1 a0 channel addressed 00 ain1 01 ain2 10 ain3 11 ain4 table 1. multiplexer truth table cs5505/6/7/8 14 ds59f4 cs5505/6/7/8 14 ds59f5
ain1. the bp/ up pin is not a latched input. the bp/ up pin controls how the output word from the digital filter is processed. in bipolar mode the output word computed by the digital filter is offset by 8000h in the 16-bit cs5505/7 or 80000h in 20-bit cs5506/8 (see understanding converter calibration). bp/ up can be changed after a conversion is started as long as it is stable for 82 clock cycles of the conversion period prior to drdy falling. if one wishes to intermix measurement of bipolar and unipolar signals on various input channels, it is best to switch the bp/ up pin immediately after drdy falls and leave bp/ up stable until drdy falls again. if the converter is beginning a conversion starting from the standby state, bp/ up can be changed at the same time as a0 and a1. the digital filter in the cs5505/6/7/8 has a fi- nite impulse response and is designed to settle to full accuracy in one conversion time. there- fore, the multiplexer can be changed at the conversion rate. if conv is left high, the cs5505/6/7/8 will per- form continuous conversions on one channel. the conversion time will be 1622 clock cycles. if conversion is initiated from the standby state, there may be up to two xin clock cycles of un- certainty as to when conversion actually begins. this is because the internal logic operates at one half the external clock rate and the exact phase of the internal clock may be 180 out of phase relative to the xin clock. when a new conver- sion is initiated from the standby state, it will take up to two xin clock cycles to begin. actual conversion will use 1624 clock cycles before drdy goes low to indicate that the serial port has been updated. see the serial interface logic section of the data sheet for information on read- ing data from the serial port. in the event the a/d conversion command (conv going positive) is issued during the con- version state, the current conversion will be terminated and a new conversion will be initi- ated. voltage reference the cs5505/6/7/8 uses a differential voltage ref- erence input. the positive input is vref+ and the negative input is vref-. the voltage be- tween vref+ and vref- can range from 1 volt minimum to 3.6 volts maximum. the gain slope will track changes in the reference without re- calibration, accommodating ratiometric applications. the cs5505/6/7/8 include an on-chip voltage reference which outputs 2.5 volts on the vre- fout pin. this voltage is referenced to the va+ pin and will track changes relative to va+. the vrefout output requires a 0.1 f capaci- tor connected between vrefout and va+ for stability. when using the internal reference, the vrefout signal should be connected to the vref- input and the vref+ pin should be con- nected to the va+ supply. the internal voltage reference is capable of sourcing 3 a maximum and sinking 50 a maximum. if a more precise reference voltage is required, an external voltage reference should be used. if an external voltage reference is used, the vrefout pin of the in- ternal reference should be connected directly to va-. it cannot be left open unless the 0.1 f ca- pacitor is in place for stability. cs5505/6/7/8 va+ vref+ vref- vrefout va- 2.5v -va +va lt1019, ref43 or lm368 figure 5. external reference connections cs5505/6/7/8 ds59f4 15 cs5505/6/7/8 ds59f5 15
external reference voltages can range from 1.0 volt minimum to 3.6 volts maximum. the com- mon mode voltage range of the external reference can allow the reference to lie at any voltage between the va+ and va- supply rails. figures 5 and 6 illustrate how the cs5505/6/7/8 converters are connected for external and for in- ternal voltage reference use, respectively. analog input range the analog input range is set by the magnitude of the voltage between the vref+ and vref- pins. in unipolar mode the input range will equal the magnitude of the voltage reference. in bipo- lar mode the input voltage range will equate to plus and minus the magnitude of the voltage ref- erence. while the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs vref+ and vref- stay within the supply volt- ages for the a/d. the differential input voltage can also have any common mode value as long as the maximum signal magnitude stays within the supply voltages. the a/d converter is intended to measure dc or low frequency inputs. it is designed to yield ac- curate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter. for example, with a 3.0 volt reference in unipolar mode, the converter will accurately convert an input dc signal up to 3.0 volts with up to 15% overrange for 60 hz noise. a 3.0 volt dc signal could have a 60 hz component which is 0.5 volts above the maxi- mum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (xin = 32.768 khz). this assumes that the signal plus noise ampli- tude stays within the supply voltages. the cs5505/6/7/8 converters output data in bi- nary format when converting unipolar signals and in offset binary format when converting bi- polar signals. table 2 outlines the output coding for the 16-bit cs5505/7 and the 20-bit cs5506/8 in both unipolar and bipolar measurement modes. cs5505 and cs5507 (16 bit) cs5506 and cs5508 (20 bit) unipolar input voltage output codes bipolar input voltage unipolar input voltage output codes bipolar input voltage >(vref - 1.5 lsb) ffff >(vref - 1.5 lsb) >(vref - 1.5 lsb) fffff >(vref - 1.5 lsb) vref - 1.5 lsb ffff fffe vref - 1.5 lsb vref - 1.5 lsb fffff ffffe vref - 1.5 lsb vref/2 - 0.5 lsb 8000 7fff -0.5 lsb vref/2 - 0.5 lsb 80000 7ffff -0.5 lsb +0.5 lsb 0001 0000 -vref + 0.5 lsb +0.5 lsb 00001 00000 -vref + 0.5 lsb <(+0.5 lsb) 0000 <(-vref + 0.5 lsb) <(+0.5 lsb) 00000 <(-vref + 0.5 lsb) note: vref = (vref+) - (vref-); table excludes common mode voltage on the signal and reference inputs. table 2. output coding -va +va 0.1 f cs5505/6/7/8 va+ vref+ vref- vrefout va- figure 6. internal reference connections cs5505/6/7/8 16 ds59f4 cs5505/6/7/8 16 ds59f5
understanding converter calibration calibration can be performed at any time. a calibration sequence will minimize offset errors and set the gain slope scale factor. the delta- sigma modulator in the converter is a differential modulator. to calibrate out offset error, the converter internally connects the modulator dif- ferential inputs to an internal vref- voltage and measures the 1s density output from the modu- lator. it stores the digital code representation for this 1s density in sram and remembers this code as being the zero scale point for the a/d conversion. the converter then connects the negative modulator differential input to the vref- input and the positive modulator differ- ential input to the vref+ voltage. the 1s density output from the modulator is then re- corded. the converter uses the digital representation of this 1s density along with the digital code for the zero scale point and calcu- lates a gain scale factor. the gain scale factor is stored in sram and used for calculating the proper output codes during conversions. the states of a0, a1 and bp/ up are ignored during calibration but should remain stable throughout the calibration period to minimize noise. when conversions are performed in unipolar mode or in bipolar mode, the converter uses the same calibration factors to compute the digital output code. the only difference is that in bipo- lar mode the on-chip microcontroller offsets the computed output word by a code value of 8000h (16-bit) or 80000h (20-bit) and multi- plies the lsb size by two. this means that the bipolar measurement range is not calibrated from full scale positive to full scale negative. instead it is calibrated from the bipolar zero scale point to full scale positive. the slope factor is then extended below bipolar zero to accommodate the negative input signals. the converter can be used to convert both unipolar and bipolar signals by changing the bp/ up pin. recalibration is not required when switching between unipolar and bipolar modes. converter performance the cs5505/6/7/8 a/d converters have excellent linearity performance. calibration minimizes the errors in offset and gain. the cs5505/7 devices have no missing code performance to 16-bits. the cs5506/8 devices have no missing code performance to 20-bits. figure 7 illustrates the dnl of the 16-bit cs5505. the converters achieve common mode rejection (cmr) at dc of 105 db typical, and cmr at 50 and 60 hz of 120 db typical. the cs5505/6/7/8 can experience some drift as temperature changes. the cs5505/6/7/8 use chopper-stabilized techniques to minimize drift. measurement errors due to offset or gain drift can be eliminated at any time by recalibrating the converter. 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 7. cs5505 differential nonlinearity plot. cs5505/6/7/8 ds59f4 17 cs5505/6/7/8 ds59f5 17
analog input impedance considerations the analog input of the cs5505/6/7/8 can be modeled as illustrated in figure 8 (the model ig- nores the multiplexer switch resistance). capacitors (15 pf each) are used to dynamically sample each of the inputs (ain+ and ain-). every half xin cycle the switch alternately con- nects the capacitor to the output of the buffer and then directly to the ain pin. whenever the sample capacitor is switched from the output of the buffer to the ain pin, a small packet of charge (a dynamic demand of current) is re- quired from the input source to settle the voltage of the sample capacitor to its final value. the voltage on the output of the buffer may differ up to 100 mv from the actual input voltage due to the offset voltage of the buffer. timing allows one half of a xin clock cycle for the voltage on the sample capacitor to settle to its final value. the equation which defines the settling time is: v e = v max e ? t ? rc where ve is the final settled value, v max is the maximum error voltage value of the input signal, r is the value of the input source resistance, c is the 15 pf sample capacitor plus the value of any stray or additional capacitance at the input pin. the value of t is equal to 1/(2xin). v max occurs the instant the sample capacitor is switched from the buffer output to the ain pin. prior to switching, ain has an error estimated as being less than or equal to v e . v max is equal to the prior error (v e ) plus the additional error from the buffer offset. the estimate for v max is: v max = v e + 100mv 15pf ( 15pf + c ext ) where c ext is the combination of any external or stray capacitance. from the settling time equation, an equation for the maximum acceptable source resistance is de- rived. rs max = ? 1 2xin ( 15pf + c ext ) ln ? ? ? ? ? v e v e + 15pf ( 100mv ) ( 15pf + c ext ) ? ? ? ? ? this equation assumes that the offset voltage of the buffer is 100 mv, which is the worst case. the value of ve is the maximum error voltage which is acceptable. for a maximum error voltage (ve) of 10 v in the cs5505 (1/4lsb at 16-bits) and 600 nv in the cs5506 (1/4lsb at 20-bits), the above equa- tion indicates that when operating from a 32.768 khz xin, source resistances up to 110 k ? in the cs5505 or 84 k ? in the cs5506 are acceptable in the absence of external capaci- tance (c ext = 0). if higher input source resistances are desired the master clock rate can be reduced to yield a longer settling time. the vref+ and vref- inputs have nearly the same structure as the ain+ and ain- inputs. therefore, the discussion on analog input imped- ance applies to the voltage reference inputs as well. + - 15 pf v os < 100 mv + - v os < 100 mv internal bias voltage 15 pf ain+ ain- cs5505/6/7/8 figure 8. analog input model cs5505/6/7/8 18 ds59f4 cs5505/6/7/8 18 ds59f5
digital filter characteristics the digital filter in the cs5505/6/7/8 is the com- bination of a comb filter and a low pass filter. the comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence frequencies (50 and 60 hz and their multiples) when the cs5505/6/7/8 is clocked at 32.768 khz. figures 9, 10 and 11 illustrate the magnitude and phase characteristics of the filter. figure 9 illustrates the filter attenuation from dc to 260 hz. at exactly 50, 60, 100, and 120 hz the filter provides over 120 db of rejection. ta- ble 3 indicates the filter attenuation for each of the potential line interference frequencies when the converter is operating with a 32.768 khz clock. the converter yields excellent attenuation of these interference frequencies even if the fun- damental line frequency should vary 1% from its specified frequency. the -3 db corner fre- quency of the filter when operating from a 32.768 khz clock is 17 hz. figure 11 illustrates that the phase characteristics of the filter are pre- cisely linear phase. 0 5 10 15 20 25 30 35 40 45 50 frequency (hz) -180 -135 -90 -45 0 45 90 135 180 phase (degrees) xin = 32.768 khz figure 11. filter phase plot to 50 hz 0 5 10 15 20 25 30 35 40 45 50 frequency (hz) -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) flatness db -0.010 -0.041 -0.093 -0.166 -0.259 -0.510 -0.667 -0.846 -1.047 -3.093 1 2 3 4 5 6 7 8 9 10 17 xin = 32.768 khz frequency -0.374 figure 10. filter magnitude plot to 50 hz frequency (hz) notch depth (db) frequency (hz) minimum attenuation (db) 50 125.6 50 1% 55.5 60 126.7 60 1% 58.4 100 145.7 100 1% 62.2 120 136.0 120 1% 68.4 150 118.4 150 1% 74.9 180 132.9 180 1% 87.9 200 102.5 200 1% 94.0 240 108.4 240 1% 104.4 table 3. filter notch attenuation (xin = 32.768 khz) 0 0 40 198.97 80 397.95 120 596.92 160 795.10 200 993.87 240 1193.85 frequency (hz) -160 -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) xin = 32.768 khz x1 x2 x1 = 32.768khz x2 = 163.00khz figure 9. filter magnitude plot to 260 hz cs5505/6/7/8 ds59f4 19 cs5505/6/7/8 ds59f5 19
if the cs5505/6/7/8 is operated at a clock rate other than 32.768 khz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. therefore, opti- mum rejection of line frequency interference will occur with the cs5505/6/7/8 running at 32.768 khz. the cs5505/6/7/8 can be used with external clock rates from 30 khz to 163 khz. anti-alias considerations for spectral measurement applications input frequencies greater than one half the out- put word rate (conv = 1) may be aliased by the converter. to prevent this, input signals should be limited in frequency to no greater than one half the output word rate of the converter (when conv =1). frequencies close to the modulator sample rate (xin/2) and multiples thereof may also be aliased. if the signal source includes spectral components above one half the output word rate (when conv = 1) these com- ponents should be removed by means of low- pass filtering prior to the a/d input to prevent aliasing. spectral components greater than one half the output word rate on the vref inputs (vref+ and vref-) may also be aliased. fil- tering of the reference voltage to remove these spectral components from the reference voltage is desirable. crystal oscillator the cs5505/6/7/8 is designed to be operated us- ing a 32.768 khz "tuning fork" type crystal. one end of the crystal should be connected to the xin input. the other end should be attached to xout. short lead lengths should be used to minimize stray capacitance. figure 12 illustrates the gate oscillator, and a simplified version of the control logic used on the chip. over the industrial temperature range (-40 to +85 c) the on-chip gate oscillator will oscillate start conversion d q clk d q clk input mux decoder 4 3 2 1 t q modulator sample clock xtl=32.768 khz a0 a1 conv cs5505/6 cal d q clk d q clk start calibration s q s q r r r channel a0 a1 1 1 0 0 1 0 1 0 10 m ? 22.5 pf 15 pf gm ~ ~ 19 umho xout xin figure 12. gate oscillator and control logic cs5505/6/7/8 20 ds59f4 cs5505/6/7/8 20 ds59f5
with other crystals in the range of 30 khz to 53 khz. over the military temperature range (- 55 to +125 c) the on-chip gate oscillator is designed to work only with a 32.768 khz crys- tal. the chip will operate with external clock frequencies from 30 khz to 163 khz . over all temperature ranges. the 32.768 khz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. to maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 to +60 c) by the manufacturers. appli- cations of these crystals with the cs5505/6/7/8 do not require tight initial tolerance or low tempco drift. therefore, a lower cost crystal with looser initial tolerance and tempco will generally be adequate for use with the cs5505/6/7/8 con- verters. also check with the manufacturer about wide temperature range application of their standard crystals. generally, even those crystals specified for limited temperature range will op- erate over much larger ranges if frequency stability over temperature is not a requirement. the frequency stability can be as bad as 3000 ppm over the operating temperature range and still be typically better than the line frequency (50 or 60 hz) stability over cycle to cycle during the course of a day. there are crystals available for operation over the military temperature range (-55 to +125 c). see the appendix for suppliers of 32.768 khz crystals. serial interface logic the digital filter in the cs5505/6/7/8 takes 1624 clock cycles to compute an output word once a conversion begins. at the end of the conversion cycle, the filter will attempt to update the serial port. two clock cycles prior to the update drdy will go high. when drdy goes high just prior to a port update it checks to see if the port is either empty or unselected ( cs = 1). if the port is empty or unselected, the digital filter will update the port with a new output word. when new data is put into the port drdy will go low. data can be read from the serial port in either of two modes. the m/slp pin determines which serial mode is selected. serial port mode selec- tion is as follows: ssc (synchronous self-clocking) mode; m/slp = vd+, or sec (synchronous external clocking) mode; m/slp = dgnd. timing dia- grams which illustrate the ssc and sec timing are in the tables section of this data sheet. synchronous self-clocking mode the serial port operates in the ssc mode when the m/slp pin is connected to the vd+ pin on the part. in ssc mode the cs5505/6/7/8 fur- nishes both the serial output data (sdata) and the serial clock (sclk). when the serial port is updated at the end of a conversion, drdy falls. if cs is low, the sdata and sclk pins will come out of the high impedance state two xin clock cycles after drdy falls. the msb data bit will be presented for two cycles of xin clock. the sclk signal will rise in the middle of the msb data bit. when sclk then returns low the (msb - 1) bit will appear. subsequent data bits will be output on each falling edge of sclk until the lsb data bit is output. after the lsb data bit is output, the sclk will fall at which time both the sdata and sclk outputs will return to the high impedance output state. drdy will return high at this time. if cs is taken low after drdy falls, the msb data bit will appear within two xin clock cycles after cs is taken low. cs need not be held low for the entire data output. if cs is returned high during a data bit the port will complete the out- put of that bit and then go into the hi-z state. the port can be reselected any time prior to the completion of the next conversion ( drdy fall- ing) to allow the remaining data bits to be output. cs5505/6/7/8 ds59f4 21 cs5505/6/7/8 ds59f5 21
synchronous external-clocking mode the serial port operates in the sec mode when the m/slp pin is connected to the dgnd pin. sdata is the output pin for the serial data. when cs goes low after new data becomes available ( drdy goes low), the sdata pin comes out of hi-z with the msb data bit pre- sent. sclk is the input pin for the serial clock in the sec mode. if the msb data bit is on the sdata pin, the first rising edge of sclk en- ables the shifting mechanism. this allows the falling edges of sclk to shift subsequent data bits out of the port. note that if the msb data bit is output and the sclk signal is high, the first falling edge of sclk will be ignored be- cause the shifting mechanism has not become activated. after the first rising edge of sclk, each subsequent falling edge will shift out the serial data. once the lsb is present, the falling edge of sclk will cause the sdata output to go to hi-z and drdy to return high. the serial port register will be updated with a new data word upon the completion of another conversion if the serial port has been emptied, or if the cs is inactive (high). cs can be operated asynchronously to the drdy signal. the drdy signal need not be monitored as long as the cs signal is taken low for at least two xin clock cycles plus 200 ns prior to sclk being toggled. this ensures that cs has gained control over the serial port. sleep mode the cs5505/6/7/8 devices offer two methods of putting the device into a sleep condition to conserve power. calibration words will be re- tained in sram during either sleep condition. the m/slp pin can be put into the sleep threshold to lower the operating power used by the device to about 1% of nominal. alternately, the clock into the xin pin can be stopped. this will lower the power consumed by the converter to about 30% of nominal. in both cases, the converter must go through a wake-up sequence prior to conversions being initiated. this wake- up sequence includes the 10 msec. (typ.) power-on-reset delay, the start-up of the oscilla- tor (unless an external clock is used), and the 1800 clock cycle wake-up delay after the clock begins. when coming out of the sleep condi- tion, the converter will latch the a0 and a1 inputs. figure 13 illustrates how to use a gate and resis- tors to bias the m/slp pin into the sleep threshold region when using the converter in the ssc mode. to use the sec mode return resistor r1 to dgnd instead of the supply. when in the sec mode configuration the cs5505/6/7/8 will enter the sleep threshold when the logic control input is a logic 1 (vd+). note that large resistors can be used to conserve power while in sleep. the input leakage of the pin is typically less than 1 a even at 125 c, although the worst case specification tables indicate a leakage of 10 a maximum. power supplies and grounding the analog and digital supply pins to the cs5505/6/7/8 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. note that there is no m/slp cs5505/6/7/8 * '1' = ssc mode '0' = sleep r 1 control input r 2 vd+ * tie r to dgnd for sec mode; control input logic inverts. 1 0.01 f r = 499k, v + = 5v; r = 590k, v + = 3.3v 1 1 dd 499k 1% 1% ** ** figure 13. sleep threshold control cs5505/6/7/8 22 ds59f4 cs5505/6/7/8 22 ds59f5
analog ground pin. no analog ground pin is re- quired because the inputs for measurement and for the voltage reference are differential and re- quire no ground. in the digital section of the chip the supply current flows into the vd+ pin and out of the dgnd pin. as a cmos device, the cs5505/6/7/8 requires that the supply volt- age on the va+ pin always be more positive than the voltage on any other pin of the device. if this requirement is not met, the device can latch-up or be damaged. in all circumstances the va+ voltage must remain more positive than the vd+ or dgnd pins; vd+ must remain more positive than the dgnd pin. the following power supply options are possi- ble: va+ = +5v to +10v, va- = 0v, vd+ = +5v va+ = +5v, va- = -5v, vd+ = +5v va+ = +5v, va- = 0v to -5v, vd+ = +3.3v the cs5505/6/7/8 cannot be operated with a 3.3v digital supply if va+ is greater than +5.5v. cs5505/6 +5v analog supply vd+ 10 ? va+ m/slp sclk sdata cal vref+ vref- dgnd va- drdy cs a0 a1 bp/up ain1+ ain- ain2+ ain3+ ain4+ conv note: xin xout to use the internal 2.5 volt reference see figure 6. *unused analog inputs should be tied to ain- 0.1 f 0.1 f 4 8 13 12 11 10 9 14 15 1 2 3 5 6 7 17 18 19 20 21 22 23 24 analog* signal sources signal ground 32.768 khz voltage reference 16 vrefout + - calibration control bipolar/ unipolar input select unused logic inputs must be connected to vd+ or dgnd. control logic serial data interface sleep mode control and output mode select optional clock source figure 14. cs5505/6 system connection diagram using external reference, single supply cs5505/6/7/8 ds59f4 23 cs5505/6/7/8 ds59f5 23
figure 14 illustrates the system connection dia- gram for the cs5505/6 using a single +5v supply. note that all supply pins are bypassed with 0.1 f capacitors and that the vd+ digital supply is derived from the va+ supply. figure 15 illustrates the cs5505/6 using dual supplies of +5 and -5v. figure 16 illustrates the cs5505/6 using dual supplies of +10v analog and +5v digital. when using separate supplies for va+ and vd+, va+ must be established first. vd+ should never become more positive than va+ under any operating condition. remember to in- vestigate transient power-up conditions, when one power supply may have a faster rise time. cs5505/6 +5v analog supply vd+ 10 ? va+ m/slp sclk sdata cal vref+ vref- dgnd va- drdy cs a0 a1 bp/up ain1+ ain- ain2+ ain3+ ain4+ conv note: xin xout to use the internal 2.5 volt reference see figure 6. *unused analog inputs should be tied to ain- 0.1 f 0.1 f 4 8 13 12 11 10 9 14 15 1 2 3 5 6 7 17 18 19 20 21 22 23 24 analog* signal sources signal ground 32.768 khz voltage reference 16 vrefout + - calibration control bipolar/ unipolar input select unused logic inputs must be connected to vd+ or dgnd. control logic serial data interface sleep mode control and output mode select optional clock source 0.1 f -5v analog supply figure 15. cs5505/6 system connection diagram using external reference, dual supplies cs5505/6/7/8 24 ds59f4 cs5505/6/7/8 24 ds59f5
cs5505/6 +10v analog supply vd+ va+ m/slp sclk sdata cal vref+ vref- dgnd va- drdy cs a0 a1 bp/up ain1+ ain- ain2+ ain3+ ain4+ conv note: xin xout (1) to use the internal 2.5 volt reference see figure 6. (2) vd+ must never exceed va+. examine power-up conditions. *unused analog inputs should be tied to ain- 0.1 f 0.1 f 4 8 13 12 11 10 9 14 15 1 2 3 5 6 7 17 18 19 20 21 22 23 24 analog* signal sources signal ground 32.768 khz voltage reference 16 vrefout + - calibration control bipolar/ unipolar input select unused logic inputs must be connected to vd+ or dgnd. control logic serial data interface sleep mode control and output mode select optional clock source (1) +5v analog supply (2) figure 16. cs5505/6 system connection diagram using external reference, dual supply, +10v analog, +5v digital schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs5505/6/7/8 ds59f4 25 cs5505/6/7/8 ds59f5 25
pin connections* 1 2 3 4 5 24 14 13 19 18 17 16 15 6 7 8 9 10 12 11 20 21 22 23 cs5505/6 1 2 3 4 5 20 15 14 13 12 11 6 7 8 9 10 16 17 18 19 cs5507/8 multiplexer selection input a0 a1 multiplexer selection input chip select cs drdy data ready convert conv sdata serial data output calibrate cal sclk serial clock input/output crystal in xin vd+ positive digital power crystal out xout dgnd digital ground serial mode/ sleep m/slp va- negative analog power bipolar/unipolar bp/ up va+ positive analog power differential analog input ain1+ vrefout voltage reference output differential analog input ain2+ vref - voltage reference input differential analog return ain- vref+ voltage reference input differential analog input ain3+ ain4+ differential analog input chip select cs drdy data ready convert conv sdata serial data output calibrate cal sclk serial clock input/output crystal in xin vd+ positive digital power crystal out xout dgnd digital ground serial mode/ sleep m/slp va- negative analog power bipolar/unipolar bp/ up va+ positive analog power differential analog input ain+ vrefout voltage reference output no connection nc vref- voltage reference input differential analog input ain- vref+ voltage reference input *pinout applies to both dip and soic cs5505/6/7/8 26 ds59f4 cs5505/6/7/8 26 ds59f5
pin descriptions pin numbers for four channel devices are in parentheses. clock generator xin; xout - crystal in; crystal out, pins 4 (5) and 5 (6). a gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be supplied into the xin pin to provide the master clock for the device. loss of clock will put the device into a lower powered state (approximately 70% power reduction). serial output i/o m/slp - serial interface mode select/ sleep, pin 6 (7). dual function pin which selects the operating mode of the serial port and provides a very low power sleep function. when m/slp is tied to the vd+ pin the serial port will operate in the synchronous self-clocking (ssc) mode. when m/slp is tied to the dgnd pin the serial port will operate in the synchronous external clocking (sec) mode. when the m/slp pin is tied half way between vd+ and dgnd the chip will enter into a very low powered sleep mode in which its calibration data will be maintained. cs - chip select, pin 1 (2). this input allows an external device to access the serial port. drdy - data ready, pin 20 (23) data ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. drdy will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the cs pin is inactive (high). sdata - serial data output, pin 19 (22). sdata is the output pin of the serial output port. data from this pin will be output at a rate determined by sclk and in a format determined by the m/slp pin. data is output msb first and advances to the next data bit on the falling edges of sclk. sdata will be in a high impedance state when not transmitting data. sclk - serial clock input/output, pin 18 (21). a clock signal on this pin determines the output rate of the data from the sdata pin. the m/slp pin determines whether sclk is an input or and output. when used as an input, it must not be allowed to float. cs5505/6/7/8 ds59f4 27 cs5505/6/7/8 ds59f5 27
control input pins cal - calibrate, pin 3 (4). when taken high the same time that the conv pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the converter. conv - convert, pin 2 (3). the conv pin initiates a calibration cycle if it is taken from low to high while the cal pin is high, or it initiates a conversion if it is taken from low to high with the cal pin low. conv latches the multiplexer selection when it transitions from low to high on the multiple channel devices. if conv is held high (cal low) the converter will do continuous conversions. a0, a1 - multiplexer selection inputs, pins (1, 24). a0 and a1 select the input channel for conversion on the multi-channel input devices. a0 and a1 are latched when conv transitions from low to high. these two inputs have pull-down resistors internal to the chip. bp/ up - bipolar/unipolar, pin 7 (8). the bp/ up pin selects the conversion mode of the converter. when high the converter will convert bipolar input signals; when low it will convert unipolar input signals. measurement and reference inputs ain+, ain-, (ain1+, ain2+, ain3+, ain4+, ain-) - differential analog inputs, pins 8, 10 (9, 10, 12, 13, 11). ain- in the cs5505/6 is a common measurement node for ain1+, ain2+, ain3+ and ain4+. vref+, vref- - differential voltage reference inputs, pins 11, 12 (14, 15). a differential voltage reference on these pins operates as the voltage reference for the converter. the voltage between these pins can be any voltage between 1.0 and 3.6 volts. voltage reference vrefout - voltage reference output, pin 13 (16). the on-chip voltage reference is output from this pin. the voltage reference has a nominal magnitude of 2.5 volts and is referenced to the va+ pin on the converter. power supply connections va+ - positive analog power, pin 14 (17). positive analog supply voltage. nominally +5 volts. va- - negative analog power, pin 15 (18). negative analog supply voltage. nominally -5 volts when using dual polarity supplies; or 0 volts (tied to system analog ground) when using single supply operation. cs5505/6/7/8 28 ds59f4 cs5505/6/7/8 28 ds59f5
vd+ - positive digital power, pin 17 (20). positive digital supply voltage. nominally +5 volts or 3.3 volts. dgnd - digital ground, pin 16 (19). digital ground. other nc - no connection, pin 9. pin should be left floating. specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a codes width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3 ? 2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal ( 1 ? 2 lsb above the voltage on the ain- pin.) when in unipolar mode (bp/ up low). units are in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal ( 1 ? 2 lsb below the voltage on the ain- pin.) when in bipolar mode (bp/ up high). units are in lsbs cs5505/6/7/8 ds59f4 29 cs5505/6/7/8 ds59f5 29
ordering guide model # of resolution linearity temperature package type number channels error range ( c) cs5505-ap 4 16-bits 0.0030% -40 to +85 24-pin 0.3" plastic dip cs5505-as 4 16-bits 0.0030% -40 to +85 24-pin 0.3" soic cs5506-bp 4 20-bits 0.0015% -40 to +85 24-pin 0.3" plastic dip cs5506-bs 4 20-bits 0.0015% -40 to +85 24-pin 0.3" soic cs5507-ap 1 16-bits 0.0030% -40 to +85 20-pin 0.3" plastic dip cs5507-as 1 16-bits 0.0030% -40 to +85 20-pin 0.3" soic cs5507-sd 1 16-bits 0.0030% -55 to +125 20-pin 0.3" cerdip cs5508-bp 1 20-bits 0.0015% -40 to +85 20-pin 0.3" plastic dip cs5508-bs 1 20-bits 0.0015% -40 to +85 20-pin 0.3" soic cs5508-sd 1 20-bits 0.0030% -55 to +125 20-pin 0.3" cerdip cs5505/6/7/8 30 ds59f4 cs5505/6/7/8 30 ds59f5 ordering information environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model package resolution liearity error channels temperature cs5505-ap 24-pin plastic dip 16 bits 0.0030% 4 -40 to +85 c cs5505-as 24-pin soic cs5505-asz (lead free) cs5506-bp 24-pin plastic dip 20 bits 0.0015% cs5506-bs 24-pin soic CS5506-BSZ (lead free) cs5507-ap 20-pin plastic dip 16 bits 0.0030% 1 cs5507-as 20-pin soic cs5507-asz (lead free) cs5508-bp 20-pin plastic dip 20 bits 0.0015% cs5508-bs 20-pin soic cs5508-bsz (lead free) model number peak reflow temp msl rating* max floor life cs5505-ap 260 c 1 no limit cs5505-as 240 c 2 365 days cs5505-asz (lead free) 260 c 3 7 days cs5506-bp 260 c 1 no limit cs5506-bs 240 c 2 365 days CS5506-BSZ (lead free) 260 c 3 7 days cs5507-ap 260 c 1 no limit cs5507-as 240 c 2 365 days cs5507-asz (lead free) 260 c 3 7 days cs5508-bp 260 c 1 no limit cs5508-bs 240 c 2 365 days cs5508-bsz (lead free) 260 c 3 7 days
appendix the following companies provide 32.768 khz crystals in many package varieties and temperature ranges. fox electronics 5570 enterprise parkway fort meyers, fl 33905 (813) 693-0099 micro crystal division / smh 702 west algonquin road arlington heights, il 60005 (708) 806-1485 saronix 4010 transport street palo alto, california 94303 (415) 856-6900 statek 512 north main orange, california 92668 (714) 639-7810 iqd ltd. north street crewkerne somerset ta18 7ak england 01460 77155 mr. pierre hersberger microcrystal/div. eta s.a. schild-rust-strasse 17 grenchen ch-2540 switzerland 065 53 05 57 taiwan xtal corp. 5f. no. 16, sec 2, chung yang s. rd. reitou, taipei, taiwan r. o. c. tel: 02-894-1202 fax: 02-895-6207 interquip limited 24/f million fortune industrial centre 34-36 chai wan kok street, tsuen wan n t tel: 4135515 fax: 4137053 s& t enterprises, ltd. rm 404 blk b sea view estate north point, hong kong tel: 5784921 fax: 8073126 mr. darren mcleod hy-q international pty. ltd. 12 rosella road, frankson, 3199 victoria, australia tel: 61-3-783 9611 fax: 61-3-783 9703 cs5505/6/7/8 ds59f4 31 cs5505/6/7/8 ds59f5 31 revision history revision date changes f4 mar 1995 first final release f5 aug 2005 updated device ordering info. updated legal notice. added msl data.. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
? notes ? cs5505/6/7/8 32 ds59f5 - notes -
33 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5505/6/7/8 evaluation board for cs5505/6/7/8 series of adcs features l operation with on-board 32.768 khz crystal or off-board clock source l jumper selectable: - ssc mode; sec mode; sleep l dip switch selectable: - bp/up mode; a0, & a1 channel selection l on-board precision voltage reference l access to all digital control pins l on-board patch area description the cdb5505/5506/5507/5508 is a circuit board de- signed to provide quick evaluation of the cs5505/6/7/8 series of a/d converters. the board can be configured to evaluate the cs5505/6/7/8 in either ssc (synchronous self-clocking) or sec (synchronous external-clocking) serial port mode. the board allows access to all of the digital interface pins of the cs5505/6/7/8 chip. ordering information cdb5505 evaluation board cdb5506 evaluation board cdb5507 evaluation board cdb5508 evaluation board i ain4+ ain3+ ain2+ ain1+ ain- +5v gnd -5v cs5505/6/7/8 clki n vref h e a d e r b u f f e r s mar 95 ds59db2 copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cdb5505/6/7/8 evaluation board for cs 5505/6/7/8 series of adcs aug ?05 ds59db3
introduction the cdb5505/6/7/8 evaluation board provides a quick means of testing the cs5505/6/7/8 series a/d converters. the cs5505/6/7/8 converters require a minimal amount of external circuitry. the evaluation board comes configured with the a/d converter chip operating from a 32.768 khz crystal and with an off-chip precision 2.5 volt reference. the board provides access to all of the digital interface pins of the cs5505/6/7/8 chip. the board is configured for operation from +5 and -5 volt power supplies, but can be operated from a single +5 volt supply if the -5v binding post is shorted to the gnd binding post. evaluation board overview the board provides a complete means of making the cs5505/6/7/8 a/d converter chip function. the user must provide a means of taking the output data from the board in serial format and using it in his system. figure 1 illustrates the schematic for the board. the board comes configured for the a/d con- verter chip to operate from the 32.768 khz watch crystal. a bnc connector for an external clock is provided on the board. to connect the external bnc source to the converter chip, a cir- cuit trace must be cut. then a jumper must be inserted in the proper holes to connect the xin pin of the converter to the input line from the bnc. the bnc input is terminated with a 50 ? resistor. remove this resistor if driving from a logic gate. see the schematic in figure 1. the board comes with the a/d converter vref+ and vref- pins hard-wired to the 2.5 volt bandgap voltage reference ic on the board. the vref+ and vref- pins can be con- nected to either the on chip reference or an off-board reference if the connections (2a and 2b) to the bandgap ic are cut. note that the pin-out of the cs5505/6/7/8 series chips allows the 20-pin single channel devices to be plugged into the 24-pin, four channel foot- print. see figure 2 which illustrates the footprint compatibility. prior to powering up the board, select the serial port operating mode with the appropriate jumper on the m/slp header. the device can be oper- ated in either the ssc (synchronous self-clocking) or the sec (synchronous exter- nal clocking) mode. see the device data sheet for an explanation of these modes. all of the control pins of the cs5505/6/7/8 are available at the j1 header connector. buffer ics u2 and u3 are used to buffer the converter for interface to off-board circuits. the buffers are used on the evaluation board only because the exact loading and off-board circuitry is un- known. most applications will not require the buffer ics for proper operation. to put the board in operation, select either bipo- lar or unipolar mode with dip switch s2. then press the cal pushbutton after the board is powered up. this initiates calibration of the con- verter which is required before measurements can be taken. to select an input channel on the four channel devices, use dip switch s2 to select the inputs a1 a0 channel addressed 00 ain1 01 ain2 10 ain3 11 ain4 table 1. multiplexer truth table cs5505/6/7/8 34 ds59db2 cdb5505/6/7/8 34 ds59db3
figure 1. adc connections 0.01 f c6 0.1 f 1a 1b 2a 2b 3a c8 0.1 f 6 5 4 2 lt1019 -2.5 v +5 c9 0.1 f external vref + _ r8 25k 3b va+ va- dgnd vd+ xin xout m/slp bp/up sclk sdata cal conv cs a0 a1 drdy vrefout vref+ vref- 16 14 15 11 7 8 21 22 23 24 1 2 3 4 10 r9 c10 0.1 f 17 20 vd+ +5 c7 0.1 f c11 0.01 f cal r11 100k 18 19 0.1 f y1 c1 -5 32.768 khz r2 r3 50 clkin 5 6 tp15 200 ain4+ 13 r7 ain4+ tp3 402 ain3+ 12 r6 ain3+ tp4 402 ain2+ 10 r5 ain2+ tp5 402 ain1+ 9 r4 ain1+ tp6 402 ain- r13 r12 100k ain- c12 0.01 f c13 0.01 f c14 0.01 f c15 402 100k 100k 100k 100k r28 r29 r30 r31 r27 r26 c19 c20 1k 1k 10nf 10nf u1 cs5505 cs5506 cs5507 or cs5508 sleep ssc sec vd+ u3c r14 100k r15 100k r21 47k vd+ u3d 7 8 10 9 tp14 13 11 12 vd+ r16 100k tp13 u3b u3a 5 6 4 3 1 2 vd+ c18 0.1 f 14 sclki sclko sdata drdy a1 a0 cs conv cal u2f 8 15 14 u2e 12 11 u2d 10 9 u2c 6 7 u2b 4 5 u2a 3 r20 r19 r18 47k r17 47k vd+ vd+ c17 0.1 f 2 1 tp12 tp11 tp7 tp8 tp9 tp10 r1 100k sclk drdy sdata +5 c16 10 f r22 10 + j2 j1 r10 20k u2 74hc4050 u3 74hc125 vd+ 100k vd+ 100k r25 100k r24 100k r23 100k s2 a1 a0 conv bp/up bp/up +5 +5 +5v -5v gnd c5 c4 0.1 f +5 - 5 + c2 10 f c3 + 10 f 0.1 f d2 d1 6.8v 6.8v agnd dgnd cs5505/6/7/8 ds59db2 35 cdb5505/6/7/8 ds59db3 35
for a0 and a1 (see table 1). once a0 and a1 are selected, the conv switch (s2-3) must be switched on (closed) and then open to cause the conv signal to transition low to high. this latches the a0 and a1 channel selection into the converter. with conv high (s2-3 open) the converter will convert continuously. figures 3 and 4 illustrate the evaluation board layout while figure 5 illustrates the component placement (silkscreen) of the evaluation board. 1 2/1 3/2 4/3 5/4 6/5 7/6 8/7 9/8 10/9 11/10 12 13 11/14 24 20/23 19/22 18/21 17/20 16/19 15/18 14/17 13/16 12/15 cs5505/6 cs5507/8 figure 2. cs5505/6 and cs5507/8 pin layouts a0 a1 cs drdy conv sdata cal sclk xin vd+ xout dgnd m/slp va- bu/up va+ ain1+ vrefout ain2+/nc vref- ain- vref+ ain3+ ain4+ cs5505/6/7/8 36 ds59db2 cdb5505/6/7/8 36 ds59db3
figure 3. top ground plane layer (not to scale) cs5505/6/7/8 ds59db2 37 cdb5505/6/7/8 ds59db3 37
figure 4. bottom trace layer (not to scale) cs5505/6/7/8 38 ds59db2 cdb5505/6/7/8 38 ds59db3
figure 5. silk screen layer (not to scale) cs5505/6/7/8 ds59db2 39 cdb5505/6/7/8 ds59db3 39
cdb5505/6/7/8 40 ds59db3 revision history revision date changes db2 mar 1995 first release f5 aug 2005 updated legal notice. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products s urgically implanted into the body, automotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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